Co-patterning thin-film resistors of different compositions with a conductive hard mask and method for same

ABSTRACT

A first thin film resistor formed by direct etch or lift off on a first dielectric layer that covers an integrated circuit in a substrate. A second thin film resistor comprised of a different material than the first resistor, formed by direct etch or lift off on the first dielectric layer or on a second dielectric layer over the first dielectric layer. The first and second thin film resistors are interconnected with another electronic device such as other resistors or the integrated circuit.

This application is a national stage application of PCT/US98/02855,filed Feb. 12, 1998, which is a CIP U.S. application Ser. No. 08/799,793filed Feb. 12, 1997, now U.S. Pat. No. 5,976,944.

FIELD OF THE INVENTION

The invention relates in general to integrated circuits with thin filmresistors.

BACKGROUND OF THE INVENTION

Thin-film resistors are generally considered to be more precise thanresistors made by diffusion or by deposited polysilicon. This is due tothe superior (lower) temperature coefficient of resistivity, and voltagecoefficient of thin-film resistors, when compared to diffused resistorsand polysilicon resistors. Also, thin-film resistors are formed muchlater in the process flow (usually just prior to the interconnectmetallization deposition), than diffused resistors and polysiliconresistors. The effects of subsequent process steps on the properties ofa thin-film resistor are thus minimized. In a typical thin film process,a dielectric layer is deposited over the semiconductor substrate, thinfilm resistor material is uniformly deposited on the dielectric layer,and the thin film resistor material is patterned into a geometricconfiguration that yields the desired resistance value. Thin filmresistors are trimmed precisely by a laser trimmer to within a verysmall deviation from the desired resistance value.

Thin film, trimmable resistors may be used in high/low power analog andlow power digital integrated circuits. In the past, integrated circuitshave generally restricted the devices in any given circuit to eitherhigh/low power analog or low power digital applications. However, moderncircuits integrate both analog and digital applications on a singlechip. See, for example, U.S. Pat. No. 5,369,309, the entire disclosureof which is here and incorporated by reference. That patent describes ananalog to digital converter and describes the simultaneous fabricationof high power and low power devices in a substrate. Precision thin filmresistors are used to manufacture analog to digital converters, band-gapreference circuits, and subscriber line interface circuits (SLIC) fortelephone systems.

Until recently, telephone line cards have been typically housed atlocations where large power generators were readily available (i.e.central offices). Thus, the amount of power required for operating theSLICs contained in the line cards was relatively unimportant.

Optical fibers have very wide bandwidth and are capable of handling alarge number of signals. A large number of telephone conversationsand/or blocks of data transmission can be concentrated into a muchsmaller number of telephone cables made with optical fibers.

Unfortunately, optical fibers are unable to carry the D.C. powerrequired to operate the telephone sets. It is impractical to supplypower at the subscriber site. Such subscriber telephones would beincompatible with existing phone sets, and would depend on the powercompanies. In the event of a loss of utility power, a subscriber's phonewould not work. The problem is solved by providing remote sites withrelatively small power capabilities at several locations within theneighborhoods to compensate for the optical fiber D.C. power deficiency.With this new arrangement, signals from the central offices aretransmitted to the appropriate remote sites where the line cards (andhence the SLICs) now reside. The SLICs then provide the signals and thepower to the subscriber phones (and extensions) at the subscriber sites.

Since these remote sites have limited power generating capabilities, thepower consumed by the SLICs has become a critical factor. Thus, new SLICdesigns are expected to provide the high power required to maketelephone sets operate properly, while minimizing the power consumptionnecessary to operate the SLIC itself. Furthermore, the relief inperformance requirements that would logically follow from a closerproximity to the subscriber, have not materialized because expandedduties have been imposed on the SLIC function.

Low power applications require a material with high sheet resistancesuch as silicon chromium (sichrome, or SiCr). That material has a sheetresistance on the order of 2.0 kOhm per square. For high powerapplications, the material of choice could be nickel chromium (nichrome,or NiCr) which has a sheet resistance of about 200 Ohms per square.There is an order of magnitude of difference between the sheetresistance of sichrome and the sheet resistance of nichrome. If one useshigher power nichrome resistors for low power applications, there wouldbe an insufficient amount of substrate area to form the low powerresistors, which typically range between 10 kohms to 500 kOhms. This isespecially critical in low-power applications and in circuits thatrequire a critical ratio match for both low value resistor sets and highvalue resistor sets. In the latter case, a diffused or implantedresistor is typically used for the low value portion of the combination.A diffused resistor is made by connecting a metal interconnect (such asaluminum) to a silicon diffusion or implant through contact aperturescut through a field oxide (typically SiO₂) at the ends of the diffusionor implant. The silicon diffusion or implant serves as the resistormaterial.

As such, there remains a long felt and unfilled need to provide resistorsets in which high value resistors are precisely matched and low valueprecise resistors are also precisely matched. There is also a need forsets of high and low power resistors with very low temperaturecoefficients as well as low voltage coefficients over the operatingrange of the device. There is also a need for precision resistors withsignificantly different sheet resistance values that are formed on thesame die or wafer. There is a further need for thin film resistors ofdifferent materials formed on the same dielectric layer or formed ondifferent dielectric layers.

SUMMARY OF THE INVENTION

The foregoing needs are met by the invention. The invention provides amethod for forming first and second thin film resistors of differentfirst and second resistor materials on a first dielectric layer or onfirst and second dielectric layers. The invention forms the first andsecond thin film resistors by direct etching or lift off or by acombination of direct etching and lift off.

The invention provides a method for forming first and second thin filmresistors of respective first and second different materials on firstand second dielectric layers. The first and second dielectric layers areseparated by a metal interconnect layer, preferably aluminum. The firstresistor is formed on the first dielectric layer by either directetching or by lift off. The first dielectric layer is suitably patternedto provide apertures for the metal interconnect to contact theunderlying integrated circuit that has been formed in the substrate. Themetal interconnect layer is sputter deposited over the first dielectriclayer and over the first thin film resistor. The apertures in thedielectric layer provide alignment targets for patterning the resultingmetal interconnect layer in order to expose the first thin filmresistors which may be suitably trimmed to their desired resistance. Asecond dielectric layer is uniformly deposited over the surface and alayer of second thin film resistor material is deposited over the seconddielectric layer. The second resistor material is different from thefirst resistor material that forms the first thin film resistors. Thesecond resistor material is suitably patterned to provide the secondthin film resistors. The second dielectric layer is likewise patternedand vias are opened to at least the underlying first interconnect layer.A second interconnect layer is deposited over the second dielectriclayer and the second thin film resistors. The second interconnect layeris likewise patterned to expose the second thin film resistors. Thesecond thin film resistor and the second interconnect layer are coatedwith a passivation layer, preferably silicon nitride.

The invention provides a method for forming first and second thin filmresistors of respective first and second different materials on only afirst dielectric layer. The first thin film resistor is formed on thefirst dielectric layer by either a lift off method or a direct etchingmethod. The second thin film resistor is formed on the same firstdielectric layer by either a lift off or a direct etching method. Withthe direct etching method, a layer of a second thin film resistormaterial is uniformly deposited over the first dielectric layer and overthe first thin film resistor. Photoresist is deposited and patternedover the bulk of the second resistor material. The exposed portion ofthe second resistor material is subjected to a suitable etching agentthat is selective between the first and second resistor materials andremoves the second resistor material but does not remove the firstresistor material or removes the first resistor material at asubstantially lower rate than it removes the second resistor material.The resulting first and second thin film resistors on the firstdielectric layer are coated with a first level interconnect layer ofmetal, preferably, aluminum. The first level interconnect layer ispatterned to expose the first and second thin film resistors. The thinfilm resistors may be trimmed. A second dielectric layer is uniformlydeposited over the first interconnect layer and the first and secondthin film resistors. The second dielectric layer is patterned with viasextending at least to the first interconnect layer. The second levelinterconnect layer, (which is optional), preferably of aluminum, isuniformly deposited over the second dielectric layer. A passivationlayer, typically silicon nitride, is deposited over the second levelinterconnect layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1a-1 e show sequential steps in forming a first thin film resistorby a direct etching method;

FIGS. 2a-2 e show sequential steps in forming a first thin film resistorby a lift off method;

FIGS. 3a-3 h show sequential steps in forming a second thin filmresistor on a second dielectric layer by direct etching;

FIGS. 4a-4 d are sequential steps in forming a second thin film resistoron a second dielectric layer by a lift off method;

FIGS. 5a-5 h show sequential steps in forming first and second thin filmresistors on the same, first dielectric layer by direct etching;

FIGS. 6a-6 d show sequential steps in forming a second thin filmresistor on the same, first dielectric layer using a lift off method;

FIGS. 7a-7 e show sequential steps in forming a first coated thin filmresistor by direct etch;

FIGS. 8a-8 e show sequential steps in forming a first coated thin filmresistor by lift off;

FIGS. 9a-9 h show sequential steps in forming a second coated thin filmresistor on a different level as the first resistor by direct etch;

FIGS. 10a-10 d show sequential steps in forming a second coated thinfilm resistor on a different level as the first resistor by lift off;

FIGS. 11a-11 h show sequential steps in forming a second coated thinfilm resistor on the same level as the first resistor by direct etch;

FIGS. 12a-12 d show sequential steps in forming a second coated thinfilm resistor on the same level as the first resistor by lift off;

FIGS. 13a-13 c show sequential steps to add an interconnect metal bydirect etch; and

FIGS. 14a-14 d show sequential steps to add an interconnect metal bylift off.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1a shows a semiconductor substrate 10 comprising silicon or othersuitable semiconductor material. An integrated circuit 9 is formed inthe semiconductor substrate 10 by suitable processes. For example, theprocesses shown and described in U.S. Pat. No. 5,369,309 are suitablefor fabricating the integrated circuit 9 in substrate 10. A firstdielectric layer 12 is formed on surface 11 of the substrate 10.Dielectric layer 12 typically comprises silicon dioxide and is typicallyformed by thermal oxidation or by a chemical vapor deposition process.However, other dielectrics may be used, including but not limited tosilicon nitride and diamond. Next, as shown in FIG. 1b, a layer of afirst thin film resistor material 14 is uniformly deposited on the firstdielectric layer 12. Layer 14 may comprise nichrome, sichrome,trinitride, tantalum nitride, doped sichrome (i.e., sichrome-B,sichrome-C) or any other suitable thin film resistor material known tothose skilled in the art. The layer 14 is typically formed by anysuitable PVD process such as evaporation or sputtering.

A layer of photoresist 18 is uniformly deposited on the thin filmresistor material 14 and is patterned to the shape of the desired thinfilm resistor. The photoresist 18 (FIG. 1c) covers a portion of the thinfilm layer 14 and exposes the rest of the thin film resistor layer 14 toa suitable etching material. Photoresist is sensitive to light. For apositive photoresist, the exposed portion of the photoresist undergoes aphoto-chemical reaction, that makes it soluble in the developer, whilethe unexposed portion remains insoluble in the developer. The oppositeis true for a negative resist. All discussions herein related tophotoresist will be using a positive photoresist, although a negativephotoresist may be similarly employed. The exposed resist is removed andthe remaining photoresist is then hard baked in order to provide an etchresistant mask over the remaining portion 14 of the first thin filmresistor material. The exposed portion of the first thin film resistorlayer 14 is etched as shown in FIG. 1d. Any suitable etchant that isselective with respect to photoresist is sufficient. The etchingoperation may be isotropic or anisotropic. Upon removal of the exposedportion of layer 14, the remaining photoresist 18 is striped to leave afirst thin film resistor 14 on a first dielectric layer 12 as shown inFIG. 1e.

A lift off method is shown in FIGS. 2a-2 e. FIG. 2a shows the firstdielectric layer 12 on a substrate 10 comprising the integrated circuit9. The first dielectric layer 12 is coated with a layer of photoresist18. The photoresist 18 is suitably patterned to expose an area 20 forthe location of the thin film resistor as shown in FIG. 2b. Thephotoresist is hard baked to provide a suitable mask. As shown in FIG.2c, the exposed portion of the first dielectric layer 12 is partiallyetched to displace the exposed surface of the dielectric layer from thesurface of the photoresist. As such, it creates a large step between thetwo levels thereby exposing the sidewalls of the photoresist to a liftoff solvent. As shown in FIG. 2d, a uniform layer of first thin filmresistor material 14 is deposited over the photoresist and the exposedportion 20 of the first level dielectric. The substrate 10 is subjectedto a suitable solvent that removes the photoresist and results in thethin film resistor 14 as shown in FIG. 2e.

FIGS. 3a-3 h show a direct etching method for forming a second thin filmresistor 30 on a second dielectric layer 26 different from the firstdielectric layer 12. With reference to FIG. 3a, the first thin filmresistor 14 is formed by either the direct etch method of FIGS. 1a-1 eor by the lift off method of FIGS. 2a-2 e. It is preferred that thefirst thin film resistor 14 is formed by the direct etch method. Thefirst level dielectric layer 12 is suitably patterned to provideapertures (not shown) extending at least to surface contact regions ofthe integrated circuit 9 in the substrate 10. A metal interconnect layer22, preferably of aluminum, is suitably deposited uniformly over thefirst dielectric layer 12 and the first thin film resistor 14. Aluminumis preferably deposited by sputtering but may also be deposited byevaporative deposition. An aperture pattern (not shown) in the aluminumlayer 22 provides suitable registration marks for locating the thin filmresistor. Forming apertures and metal interconnect layers are well knownto those skilled in the art. In an earlier step, not shown, the aluminum22 is suitably patterned in order to expose the thin film resistor 14and provide the structure as shown in FIG. 3a.

The thin film resistor 14 is then covered with a second dielectric layer26 as shown in FIG. 3b. The second dielectric layer 26 is preferablysilicon dioxide but may be any suitable dielectric including but notlimited to silicon nitride and diamond.

A second layer of thin film resistor material 30 is uniformly depositedover second dielectric layer 26. See FIG. 3c. The second thin film layer30 is covered with a layer 32 of photoresist. The photoresist issuitably patterned, developed and hard baked to provide the structure asshown in FIG. 3d. That structure is etched to remove the exposedportions of layer 30 and provide the resulting structure as shown inFIG. 3e. Thereafter, the photoresist is stripped to provide the secondthin film resistor 30 on the second dielectric layer 26 as shown in FIG.3f.

In a manner similar to that described at the beginning of this method, asecond interconnect level 34 is formed over the structure of FIG. 3f.Prior to forming the interconnect layer 34, suitable vias are etched atleast through second level dielectric layer 26 and extending to thefirst level interconnect layer 22. The vias may be further etchedthrough the first dielectric layer 12 to contact the integrated circuit9. After the layer 34 is deposited, it is suitably patterned to exposedthe thin film resistor 30. A passivation dielectric layer 36, typicallysilicon nitride, is uniformly deposited over the structure as shown inFIG. 3h.

A second thin film resistor may also be formed by the lift off method asshown in FIGS. 4a-4 d. The structure shown in FIG. 4a is formed bysubstantially the same steps described in connection with FIGS. 3a and 3b. After deposition of the second dielectric layer 26, a photoresistlayer 27 is deposited over the second dielectric layer 26. A resistpattern 29 is etched into the exposed portion of the photoresist layerin order to assist the lift off process and into the second dielectriclayer 26. The resist pattern 29 is shown in FIG. 4b. Next, as shown inFIG. 4c, the uniform layer of second thin film resistor material 30 isdeposited over the structure of FIG. 4b. In a following step, thephotoresist 27 is removed by a suitable solvent thereby leaving thesecond thin film resistor 30 on the second dielectric layer 26 as shownin FIG. 4d.

Those skilled in the art will appreciate that a second interconnectlayer and a passivation layer may be formed over the structure shown inFIG. 4d in a manner substantially the same as that shown in FIGS. 3g and3 h and described above.

A method for direct etch forming the second thin film resistor on thesame, first dielectric layer as the first thin film resistor is shown inFIGS. 5a-5 h. With reference to FIG. 5a, the first thin film resistor 14is formed either by direct etching or by lift off as shown and describedin connection with either FIGS. 1a-1 e or FIGS. 2a-2 e. After formationof the first thin film resistor 14 on the first dielectric layer 12, auniform layer 30 of second thin film resistor material is deposited overthe first dielectric layer 12 and over the first thin film resistor 14.As shown in FIG. 5b, a photoresist layer 32 is uniformly deposited overthe structure of FIG. 5a. The photoresist layer 32 is suitably patternedto the shape of the desired second thin film resistor, exposedphotoresist is removed, and the remaining photoresist is hard baked toprovide a resist material over a portion of the second thin filmresistor layer 30. As shown in FIG. 5c, the exposed thin film resistorlayer 30 is removed by a suitable etching material that selectivelyetches material 30 with respect to material 14. A typical etching agentfor nichrome is an aqueous solution of ceric sulfate, and sulfuric acid.A typical etching agent for sichrome is a mixture of phosphoric, nitric,and hydrofluoric acid.

Those skilled in the art will recognize that the first thin filmresistor material 14 and the second thin film resistor material 30 aredifferent from each other. One may be nichrome and the other sichromeand either may be of another suitable material. This method will operateso long as the two layers 14, 30 are not of the same material. Next thephotoresist 32 is stripped to expose the two thin film resistors asshown in FIG. 5d. The thin film resistors 14, 30 may be suitably trimmedafter deposition of the passivation layer. Next, as shown in FIG. 5e, aninterconnect layer 22 is uniformly deposited over the first dielectriclayer and over the first and second thin film resistors, 14, 30. Asdescribed above in connection with FIG. 3, the first level dielectriclayer 12 is patterned to include apertures for the interconnect materialto contact the integrated circuit 9 in the substrate 10. The aperturepattern provides a suitable alignment target for exposing the thin filmresistors 30, 14. Next a second dielectric layer 26 is uniformlydeposited over the interconnect level 22 and the thin film resistors 30,14. The second dielectric layer 26 is patterned with suitable viasextending to at least to the first interconnect level 22 and/or to theintegrated circuit 9. As shown in FIG. 5g, a second interconnect level34 is uniformly deposited over the second dielectric layer 26. Finally,passivation layer 36, as shown in FIG. 5h, is uniformly deposited overthe second interconnect level 34.

A second thin film resistor is formed on the same first dielectric layerby a lift off method as shown in FIGS. 6a-6 d. With reference to FIG.6a, a silicon substrate 10 with a first dielectric layer has a firstthin film resistor 14 formed by either the direct etch method of FIG.1a-1 e or by the lift off method FIGS. 2a-2 e. In a first step as shownin FIG. 6a, a layer of photoresist 32 is uniformly deposited over thefirst dielectric layer 12 and over the first thin film resistor 14. Thephotoresist is patterned and hard baked to provide a suitable resistmask. Next, as shown in FIG. 6b, the exposed portion 49 of the firstlevel dielectric layer 12 is etched in order to increase the distancebetween the level of the exposed dielectric 12 and the top level of thephotoresist 32. Next a uniform layer of second thin film resistormaterial 30 is deposited over the photoresist layer 32. The result instructure is shown in FIG. 6c.

The structure of FIG. 6c is exposed to a suitable solvent to remove thephotoresist 32 and thereby expose the first and second thin filmresistors 14, 30 both on the first dielectric layer 12. First and secondinterconnect and passivation layers may be applied to the structureshown in FIG. 6d in substantially the same manner as shown and describedin connection with FIGS. 5e-5 h.

The methods disclosed in FIGS. 1-6 disclose a method wherein the metalinterconnect is in direct contact with the thin film resistors. Themethod to obtain such direct contact can sometimes damage the thin filmresistors. The damage may result from the process to remove the metallayer overlaying the thin film resistor material. One method to preventsuch damage is to change the first and second thin film resistors 14, 30to a first and second coated thin film resistors 72, 76.

Each first coated thin film resistor 72 comprises the first resistormaterial 14 and a first conductive hard mask material 70. Likewise, eachsecond coated thin film resistor 76 comprises the second resistormaterial 30 and a second conductive hard mask material 74. The first andsecond resistor materials 14, 30 are two different materials. Thedifferent materials can be nichrome, sichrome, doped sichrome,tantalum-nitride, trinitride and the like. The first and secondconductive hard mask materials 70, 74 can be the same or differentrefractory materials. Such refractory materials comprise titanium,tungsten, molybdenum or mixtures thereof. Preferably, the refractorymaterial is titanium-tungsten.

FIG. 7a shows the semiconductor substrate 10 comprising silicon or othersuitable semiconductor material. The integrated circuit 9 is formed inthe semiconductor substrate 10 by suitable processes. The firstdielectric layer 12 is formed on surface 11 of the substrate 10. Next,as shown in FIG. 7b, the layers of the first thin film resistor material14 and the first conductive mask material 70 are uniformly deposited onthe first dielectric layer 12. The layer of photoresist 18 is uniformlydeposited on the first conductive mask material 70 and is patterned tothe shape of the desired coated thin film resistor. The photoresist 18(FIG. 7c) covers a portion of the first conductive hard mask material 70and exposes the rest of the first conductive hard mask material 70 andthe first resistor material 14 underlying the exposed first conductivehard mask material 70 to a suitable etching material. The exposedportion of the first conductive hard mask material 70 and underlyingfirst resistor layer 14 is etched as shown in FIG. 7d. Upon removal ofthe exposed portion of layer 70 and underlying layer 14, the remainingphotoresist 18 is striped to leave a first coated thin film resistor 72on a first dielectric layer 12 as shown in FIG. 7e.

A lift off method is shown in FIGS. 8a-8 e. The first dielectric layer12 is coated with a layer of photoresist 18. The photoresist 18 issuitably patterned to expose an area 20 for the location of the coatedthin film resistor. The photoresist is hard baked to provide a suitablemask. As shown in FIG. 8c, the exposed portion of the first dielectriclayer 12 is partially etched to displace the exposed surface of thedielectric layer from the surface of the photoresist. As such, itcreates a large step between the two levels thereby exposing thesidewalls of the photoresist to a lift off solvent. As shown in FIG. 8d,a uniform layers of first thin film resistor material 14 and a firstconductive hard mask material 70 are deposited over the photoresist andthe exposed portion 20 of the first level dielectric. The substrate 10is subjected to a suitable solvent that removes the photoresist andresults in the coated thin film resistor 72 as shown in FIG. 8e.

FIGS. 9a-9 h show a direct etching method for forming a second coatedthin film resistor 30 on the second dielectric layer 26 different fromthe first dielectric layer 12. With reference to FIG. 9a, the firstresistor 60 is either the thin film resistor 14 or the first coated thinfilm resistor 70. The resistor 70 is formed by either the direct etchmethod of FIGS. 7a-7 e or by the lift off method of FIGS. 8a-8 e. Theresistor 14 is formed by either the direct etch method of FIGS. 1a-1 eor by the lift off method of FIGS. 2a-2 e. It is preferred that theresistor 60 is the first coated thin film resistor 72 formed by thedirect etch method. The first level dielectric layer 12 is suitablypatterned to provide apertures (not shown) extending at least to surfacecontact regions of the integrated circuit 9 in the substrate 10. Themetal interconnect layer 22, preferably of aluminum, is suitablydeposited uniformly over the first dielectric layer 12 and the firstcoated thin film resistor 72. In earlier steps, not shown, the aluminum22 is suitably patterned in order to expose portions of the first coatedthin film resistor 72 and the exposed first conductive mask material 70is removed so the aluminum 22 contacts the first coated thin filmresistor 72 through the remaining first conductive hard mask material.These earlier steps result in the structure shown in FIG. 9a.

The first coated thin film resistor 72 is then covered with the seconddielectric layer 26 as shown in FIG. 9b. The second thin film resistormaterial 30 and the conductive hard mask material 74 are uniformlydeposited over the second dielectric layer 26. See FIG. 9c. As shown inFIG. 9d, the second conductive hard mask material 74 is covered with thelayer 32 of photoresist. The photoresist is suitably patterned,developed and hard baked to provide the structure as shown in FIG. 9e.That structure is etched to remove the exposed portions of layer 74 andthe layer 30 that underlies the exposed layer 74. The resultingstructure is shown in FIG. 9f.

Thereafter, the photoresist is stripped to provide the second coatedthin film resistor 76 on the second dielectric layer 26. In a mannersimilar to that described at the beginning of this method, the secondinterconnect level 34 is formed over the structure of FIG. 9g. Prior toforming the interconnect layer 34, suitable vias are etched at leastthrough the second level dielectric layer 26 and extending to the firstlevel interconnect layer 22. The vias may be further etched through thefirst dielectric layer 12 to contact the integrated circuit 9. After thelayer 34 is deposited, it is suitably patterned to exposed the secondcoated thin film resistor 76. The exposed second conductive maskmaterial 74 is removed by conventional processes known to those skilledin the art. The interconnect layer contacts the second resistor material30 through the second conductive mask material 74 as shown in FIG. 9g. Apassivation dielectric layer 36, typically silicon nitride, is uniformlydeposited over the structure as shown in FIG. 9h.

A second coated thin film resistor 76 may also be formed by the lift offmethod as shown in FIGS. 10a-10 d. The structure shown in FIG. 10a isformed by substantially the same steps described in connection withFIGS. 1a-1 e, 2 a-2 e, 7 a-7 e and 8 a-8 e. After deposition of thesecond dielectric layer 26, the photoresist layer 27 is deposited overthe second dielectric layer 26. The resist pattern 29 is etched into theexposed portion of the photoresist layer in order to assist the lift offprocess and into the second dielectric layer 26. The resist pattern 29is shown in FIG. 10b. Next, as shown in FIG. 10c, the uniform layers ofsecond thin film resistor material 30 and second conductive hard maskmaterial 74 are deposited over the structure of FIG. 10b. In a followingstep, the photoresist 27 is removed by a suitable solvent therebyleaving the second coated thin film resistor 76 on the second dielectriclayer 26 as shown in FIG. 10d.

Those skilled in the art will appreciate that a second interconnectlayer and a passivation layer may be formed over the structure shown inFIG. 10d in a manner substantially the same as that shown in FIGS. 9gand 9 h and described above.

A method for direct etch forming the second coated thin film resistor 76on the same, first dielectric layer as the first coated thin filmresistor 72 is shown in FIGS. 11a-11 h. With reference to FIG. 11a, theresistor 60 is either the first coated thin film resistor 72 or the thinfilm resistor 14. Resistor 72 is formed either by direct etching or bylift off as shown and described in connection with either FIGS. 7a-7 eor FIGS. 8a-8 e. Resistor 14 is formed either by direct etching or bylift off as shown and described in connection with either FIGS. 1a-1 eor FIGS. 2a-2 e. Preferably, resistor 60 is the coated thin filmresistor 72 formed by direct etch.

After formation of the resistor 60 on the first dielectric layer 12, theuniform layers of the second thin film resistor material 30 and thesecond conductive mask material 74 are deposited over the firstdielectric layer 12 and over the resistor 60. As shown in FIG. 11b, thephotoresist layer 32 is uniformly deposited over the structure of FIG.11a. The photoresist layer 32 is suitably patterned to the shape of thedesired second coated thin film resistor, exposed photoresist isremoved, and the remaining photoresist is hard baked to provide a resistmaterial over a portion of the second coated thin film resistor layer76. As shown in FIG. 11c, the exposed second conductive hard maskmaterial 74 and the thin film resistor material 30 that underlies theexposed second conductive hard mask material 74 are removed by asuitable etching material that selectively etches materials 74, 30 withrespect to materials 70, 14. A typical etching agent for nichrome is anaqueous solution of ceric sulfate, and sulfuric acid. A typical etchingagent for sichrome is a mixture of phosphoric, nitric, and hydrofluoricacid.

Those skilled in the art will recognize that the first resistor material14 and the second resistor material 30 are different from each other.One may be nichrome and the other sichrome and either may be of anothersuitable material. This method will operate so long as the two layers14, 30 are not of the same material. Next the photoresist 32 is strippedto expose the coated thin film resistors 76 and resistor 60 (preferablythe coated thin film resistor 72) as shown in FIG. 11d. The coated thinfilm resistors 72, 76 may be suitably trimmed after deposition of thepassivation layer. Next, as shown in FIG. 11e, an interconnect layer 22is uniformly deposited over the first dielectric layer and over thefirst and second coated thin film resistors, 72, 76. The interconnectlayer is patterned and removed to expose portions of the first andsecond conductive mask material 70, 74. The exposed first and secondconductive mask materials 70, 74 are removed so the interconnect layerconnects to the conductive mask material on each first and second coatedthin film resistor 72, 76. As described above in connection with FIG. 9,the first level dielectric layer 12 is patterned to include aperturesfor the interconnect material to contact the integrated circuit 9 in thesubstrate 10. The aperture pattern provides a suitable alignment targetfor exposing the coated thin film resistors 72, 76. Next a seconddielectric layer 26 is uniformly deposited over the interconnect level22 and the coated thin film resistors 72, 76. The second dielectriclayer 26 is patterned with suitable vias extending to at least to thefirst interconnect level 22 and/or to the integrated circuit 9. As shownin FIG. 11g, a second interconnect level 34 is uniformly deposited andpatterned over the second dielectric layer 26. Finally, passivationlayer 36, as shown in FIG. 11h, is uniformly deposited over the secondinterconnect level 34.

A second coated thin film resistor 76 is formed on the same firstdielectric layer by a lift off method as shown in FIGS. 12a-12 d. Withreference to FIG. 12a, a silicon substrate 10 with a first dielectriclayer has a first coated thin film resistor 72 formed by either thedirect etch method of FIG. 7 or by the lift off method FIG. 8. In afirst step as shown in FIG. 12a, a layer of photoresist 32 is uniformlydeposited over the first dielectric layer 12 and over the first resistor60. The photoresist is patterned and hard baked to provide a suitableresist mask. Next, as shown in FIG. 12b, the exposed portion 49 of thefirst level dielectric layer 12 is etched in order to increase thedistance between the level of the exposed dielectric 12 and the toplevel of the photoresist 32. Next uniform layers of second thin filmresistor material 30 and second conductive hard mask material 74 aredeposited over the photoresist layer 32. The result in structure isshown in FIG. 12c.

The structure of FIG. 12c is exposed to a suitable solvent to remove thephotoresist 32 and thereby expose the first and second resistors 60, 76both on the first dielectric layer 12. First and second interconnect andpassivation layers may be applied to the structure shown in FIG. 12 insubstantially the same manner as shown and described in connection withFIGS. 11e-11 h.

An alternative embodiment to apply the interconnect layers by a directetch method is shown in FIGS. 13a-c. In FIG. 13a shows a resistor 78overlaying a dielectric layer 80. The resistor 78 is either a thin filmresistor 14, 30 or coated thin film resistor 72, 76. If the coated thinfilm resistor 72, 76 is used, the conductive mask material must beremoved from the conductive path of the resistor material. Thedielectric layer 80 is either dielectric layer 12 or 26 and is over asubstrate (not shown). A third dielectric layer 82 is deposited on theresistor 78 and the dielectric layer 80. Preferably, the thirddielectric layer is an oxide such as silicon oxide and is deposited as athin layer (around 500 Å).

Vias 84 are patterned and etched down to the terminals 86 of theresistor 78 as shown in FIG. 13b. Preferably, the via etch process doesnot damage the resistor 78 since the resistor 78 is exposed once thevias are formed.

Metal interconnect layer, like aluminum 22, is deposited, patterned andetched so the metal interconnects to the terminals 86 as shown in FIG.13c. Since the resistor 78 is encapsulated, the etch method used for themetal interconnect layer need not be selective with respect to theresistor 78 material used. The length (L) of the resistor 78 is from theinner edges 90 of the via 84.

Another alternative embodiment to apply the interconnect layers is shownin FIGS. 14a-d. In FIG. 14a shows a resistor 78 overlaying a dielectriclayer 80. A first photoresist material 92 is applied and patterned overthe dielectric layer 80 and the resistor 78 to expose portions of thedielectric layer 80 and the resistor 78, except the terminals 86 asshown in FIG. 14b. The third dielectric layer 82 is deposited on theexposed portions 80, 78. The photoresist material 92 is removed to formthe structure shown in FIG. 14c.

Metal interconnect layer, like aluminum 22, is deposited, patterned andetched so the metal interconnects to the terminals 86 as shown in FIG.14d. Since the resistor 78 is encapsulated, the etch method used for themetal interconnect layer need not be selective with respect to theresistor 78 material used. The length (L) of the resistor 78 is from theinner edges 90 of the via 84.

Having thus described the preferred embodiments of the invention, thoseskilled in the art will appreciate that further additions, changes,deletions, and alterations may be made to above described processes andstructures without departing from the spirit and the scope of theinvention as set forth in the following claims.

What we claim:
 1. An integrated circuit formed in a semiconductorsubstrate comprising a first dielectric layer formed over the integratedcircuit; a first thin film resistor of a first resistor material on thefirst dielectric material; a second thin film resistor of a secondresistor material different from the first resistor material formed onthe first dielectric material; a first conductive hard mask material onat least a portion of the top surface of the first thin film resistor toform a first coated thin film resistor; a second conductive hard maskmaterial on at least a portion of the top surface of the second thinfilm resistor to form a second coated thin film resistor; and aninterconnect metal layer patterned to interconnect at least the firstand second coated thin film resistors to the integrated circuit whereinthe interconnect metal connects to the first and second conductive hardmask materials.
 2. The circuit of claim 1, wherein the first and secondconductive hard mask materials are refractory materials.
 3. The circuitof claim 2, wherein the refractory materials comprise at least oneelement selected from the group consisting of titanium, tungsten,molybdenum and alloys thereof.
 4. The circuit of claim 3, wherein therefractory materials are titanium-tungsten.
 5. The circuit of claim 1,wherein the first and second conductive hard mask materials aredifferent.
 6. The circuit of claim 1, wherein the first and secondresistor materials comprise two different materials selected from thegroup consisting of nichrome, sichrome, sichrome-B, sichrome-C andtantalum nitride.
 7. The circuit of claim 1, wherein hard mask materialis on at least one side edge of each thin film resistor.
 8. Anintegrated circuit formed in a semiconductor substrate comprising afirst dielectric layer formed over the integrated circuit; a firstcoated thin film resistor on the first dielectric layer and comprising afirst resistor material and a first conductive hard mask material on atleast a portion of the top surface of the first resistor material; asecond dielectric layer on said first coated thin film resistor andfirst dielectric layer; a second coated thin film resistor on saidsecond dielectric layer and comprising a second resistor materialdifferent from the first resistor material and a second conductive hardmask material on at least a portion of the top surface of the secondresistor material; and one or more interconnect metal layers patternedto interconnect said first and second coated thin film resistors to theintegrated circuit.
 9. The circuit of claim 8 wherein the first andsecond conductive hard mask materials are refractory materials.
 10. Thecircuit of claim 9 wherein the refractory materials comprising at leastone element selected from the group consisting of titanium, tungsten,and molybdenum.
 11. The circuit of claim 10 wherein the refractorymaterials are titanium-tungsten.
 12. The circuit of claim 8 wherein thefirst and second co mask materials are different.
 13. The circuit ofclaim 8 wherein each of the first and second resist materials isselected from the group consisting of nichrome, sichrome, sichrome-B,sichrome-C, and tantalum nitride.
 14. The circuit of claim 8 wherein theportion of the top surface of is each of the first and second coatedthin film resistors is at least one side edge.
 15. An integrated circuitformed in a semiconductor substrate, comprising: a first dielectriclayer formed over the integrated circuit; a first thin film resistor ofa first resistor material; a second dielectric layer patterned on thefirst dielectric layer and a second thin film resistor on said seconddielectric layer; and a metal layer patterned on the first dielectriclayer and interconnecting the thin film resistors to an electronicdevice.